A 10-bit 120MS/s SAR ADC using tri-switch sampling and VCM-stable switching scheme in 40-nm CMOS

A 10-bit 120MS/s successive-approximation-register (SAR) analog-to-digital converter (ADC) in 40-nm CMOS is presented. To diminish the fluctuation of common-mode voltage (VCM) and switching energy during conversion, a VCM-stable scheme adopted without increasing design complexity to VCM buffers. Moreover, tri-switch sampling employed this design. Together with binary-scaled recombination weighting (BSRW) method, it cancels gain error non-linearity caused by parasitic input capacitor comparators. The measurement results show that reported ADC achieves an ENOB 9.3 bits sampled at 120MS/s. worst differential (DNL) integrated (INL) are both below 0.5 LSB. proposed consumes 1.08-mW power, resulting figure merit (FoM) 14.3 fJ/Conv.-step.